FIG. #_1 illustrates a memory circuit #_100 according to the prior art. The memory circuit #_100 includes a controller #_110 and DRAMs #_120a, #_120b, . . . , #_120.alpha.. The controller #_110 and the DRAMs #_120 are communicatively connected by means of a data bus #_130 and a clock bus #_140. A resistor R.sub.t #_150 ties each of the busses #_130 and #_140 to a voltage source #_160 at a threshold voltage V.sub.t.
The circuit components #_110, #_120 each includes a D latch #_1A0, a receive clock buffer #_170 and transmit clock and data drivers #_180 and #_190. The data input of the D latch #_1A0 is coupled to the data bus #_130. The clock input of the D latch is coupled to the internal clock signal output from the receive clock buffer #_230.
Digital logic implements each of the drivers #_170, #_180 and #_190. The input-output function of the drivers is essentially a threshold function.
The data bus #_130 is a read/write bidirectional link. The circuit #_100 uses the bus #_130 to transfer write data from the controller #_110 to a DRAM #_120 and to transfer read data from a DRAM #_120 to the controller #_110.
The operation of the data bus #_130 occurs at a sufficiently high speed to require timing information with both read and write data. The data clock is used to latch the data.
FIG. #_2 illustrates example clock and data signals #_210 and #_220, asserted on the clock and data busses #_140 and #_130, as well as an example internal clock signal #_230 as received in a receiving device. As FIG. #_2 illustrates, the data and clock busses #_130 and #_140 terminate to the midpoint threshold reference voltage V.sub.t.
When the memory circuit #_100 passes control among the controller #_110 and the DRAMs #_120, the device A relinquishing control disables its data output and data clock drivers #_180 and #_190. The disabling allows the busses #_130, #_140 to return to a high impedance state. The device B taking control begins driving the data and clock busses #_130, #_140.
A problem occurs, however, in the device C (which may be the same as A) receiving the data: During the (brief) period of transition of control from one circuit #_100 component #_110, #_120 to another, the clock input #_210 through the buffer #_170 can be at a high impedance state at or near the threshold voltage V.sub.t. The receiving device C may receive spurious clock edges #_250, corrupting the data received.
FIG. #_3 illustrates another memory circuit #_300 according to the prior art. The memory circuit #_300 includes a controller #_310 and DRAMs #_320a, #_320b, . . . , #_320.beta.. The controller #_310 and the DRAMs #_320 are communicatively connected by the data bus #_130 and the clock bus #_140 tied by resistors R.sub.t #_150 to the voltage source #_160.
The data bus #_130 is a read/write bidirectional link. The circuit #_300 transfers write data from the controller #_310 to a DRAM #_320 on the bus #_130 and transfers read data from a DRAM #_320 to the controller #_310 on the bus #_130.
Each of the circuit #_300 components #_310, #_320 includes a D latch #_1A0, a receive clock buffer #_340 and transmit clock and data drivers #_180 and #_190. The data input of the D latch #_1A0 is coupled to the data bus #_130. The clock input of the D latch is coupled to the internal clock signal output from the receive clock buffer #_340.
The clock input buffers #_340 have input-output functions with hysteresis. As the graph of FIG. #_6 shows, the output of a buffer #_340 depends on both the input voltage and the history of the input to the buffer.
When the memory circuit #_100 passes control among the controller #_110 and the DRAMs #_120, the device relinquishing control disables its data output drivers #_180 and data clock drivers #_190. The disabling allows the busses #_130, #_140 to return to a high impedance state. The device taking control begins driving the data and clock busses #_130, #_140.
FIG. #_6 illustrates the example data signal #_210 asserted on the data bus #_130 of the circuit #_300 and an example internal clock signal #_350 as received in a receiving device through a buffer #_340, given the clock signal #_210. As FIG. #_6 shows, the hysteretic buffer #_340 defeats the spurious clock edges #_250.
The buffers #_340, however, also defeat the predetermined matched delay of the data and clock paths using the D latch #_1A0 and the clock buffer #_170. The mismatch between clock and data also depends on the input slew rate.
Further, the hysteretic buffer #_340 has less input drive differential for equal amplitude signal. This reduces the speed potential of such a memory circuit.
According, there is a need for a memory circuit that, in operation, does not generate spurious clock edges as a clock signal approaches the high impedance state. One objective of the invention is such a memory circuit.
These and other objectives of the invention will be readily apparent to one of ordinary skill in the art on the reading of the background above and the description below.